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TPS23757
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SLVS948D – JULY 2009 – REVISED NOVEMBER 2013
Blanking - R BLNK
The TPS23757 provides a choice between internal fixed and programmable blanking periods. The blanking
period is specified as an increase in the minimum GATE on time over the inherent gate driver and comparator
delays. The default period (see the Electrical Characteristics table) is selected by connecting BLNK to RTN, and
the programmable period is set with R BLNK .
The TPS23757 blanker timing is precise enough that the traditional R-C filters on CS can be eliminated. This
avoids current-sense waveform distortion, which tends to get worse at light output loads. There may be some
situations or designers that prefer an R-C approach. The TPS23757 provides a pull-down on CS during the
GATE off time to improve sensing when an R-C filter must be used. The CS input signal should be protected
from nearby noisy signals like GATE drive and the switching MOSFET drain.
Dead Time
The TPS23757 features two switching MOSFET gate drivers to ease implementation of high-efficiency
topologies. Specifically, these include active (primary) clamp topologies and those with synchronous drivers that
are hard-driven by the control circuit. In all cases, there is a need to assure that both driven MOSFETs are not
on at the same time. The DT pin programs a fixed time period delay between the turn-off of one gate driver until
the turn-on of the next. This feature is an improvement over the repeatability and accuracy of discrete solutions
while eliminating a number of discrete parts on the board. Converter efficiency is tuned with this one repeatable
adjustment. The programmed dead time is the same for both GATE-to-GAT2 and GAT2-to-GATE transitions.
The dead time period is specified with some capacitive loading and is triggered from internal signals that are
several stages back in the driver to eliminate the effects of the gate waveform. The actual dead-time will be
somewhat dependent on the gate loading. The turnoff of GAT2 coincides with the start of the internal clock
period.
Connecting DT to V B disables GAT2, which goes to a high-impedance state.
GATE’s phase turns the main switch on when it transitions high, and OFF when it transitions low. GAT2’s phase
turns the second switch OFF when it transitions high, and on when it transitions low. Both switches should be
OFF when GAT2 is high and GATE is low. The signal phasing is shown in Figure 2 . Many topologies that use
secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer.
The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding
(swapping the leads). Use of the two gate drives is shown in Figure 1 .
FRS and Synchronization
The FRS pin programs the (free-running) oscillator frequency, and may also be used to synchronize the
TPS23757 converter to a higher frequency. The internal oscillator sets the maximum duty cycle at 78% and
controls the slope-compensation ramp circuit. Synchronization may be accomplished by applying a short pulse
(T SYNC ) of magnitude V SYNC to FRS as shown in Figure 25 . The synchronization pulse terminates the potential
on-time period, and the off-time period does not begin until the pulse terminates. Reducing the on-time reduces
the available maximum duty cycle.
APb, Startup and Power Management
APb (adapter present) is an active-low multifunction pin that indicates if
[ (1.5 V < V APD ) + (1.55 V < V PPD ≤ 8.3 V)] × (V CTL < 4 V) × (pd current limit ≠ Inrush).
The term with V CTL prevents an optocoupler connected to the secondary-side from loading V C before the
converter is started. The APD and PPD terms indicate that an adapter is plugged into the PD, and voltage is
present on them. APb permits applications which run from high-power adapters ( > 13 W) to detect their
presence and adjust the load appropriately. The usage of APb is demonstrated in Figure 1 .
Thermal Shutdown
The dc/dc controller has an OTSD that can be triggered by heat sources including the V B regulator, GATE driver,
bootstrap current source, and bias currents. The controller OTSD turns off V B , the GATE driver, and forces the
V C control into an undervoltage state.
Copyright ? 2009–2013, Texas Instruments Incorporated
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